Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings

Pirmais vāks
Andreas Krall
Springer, 2003. gada 24. okt. - 406 lappuses
This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24–26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand pro?t from the assembly of international experts in the ?eld. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in ?elds of interest led to a change of name, and this is when the present name was used for the ?rst time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop.
 

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Saturs

Invited Talk
1
Predicated Instructions for Code Compaction
17
Code Generation for a Dual Instruction Set Processor Based
33
Sheayun Lee Jaejin Lee Sang Lyul Min Jason Hiser
47
Erik Eckstein Oliver König and Bernhard Scholz
66
Reconstructing Control Flow from Predicated Assembly Code
81
Loop Optimizations
101
Stefaan Himpe Francky Catthor and Geert Deconinck
117
Code Generation for Packet Header Intrusion Analysis on the IXP1200
226
Register Allocation
240
FineGrain Register Allocation Based on a Global Spill Costs Analysis
255
Offset Assignment
270
Improving Offset Assignment through Simultaneous Variable Coalescing
285
Desiree Ottoni Guilherme Ottoni Guido Araujo and Rainer Leupers
298
Performance Analysis for Identification of SubTaskLevel Parallelism
313
Towards Superinstructions for Java Interpreters
329

Litong Song Krishna Kavi and Ron Cytron
133
Automatic Retargeting
151
Extraction of Efficient Instruction Schedulers from CycleTrue
167
System Design
182
Arshad Jhumka Neeraj Suri and Martin Hiller
198
Composable Code Generation for ModelBased Development
211
Kevin Casey David Gregg M Anton Ertl and Andrew Nisbet
344
Efficient Variable Allocation for Dual Memory Banks of DSPs
359
Cache Behavior Modeling of Codes with DataDependent Conditionals
373
A Fast Instruction Cache Optimizer
388
Author Index
403
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