Surviving the Design of a 2000 MHz RISC Microprocessor: Lessons Learned
Learn all the intricacies of the design of a 32-bit RISC microprocessor developed through the first DARPA effort to create a 200 MHz processor on a VLSI chip. This book takes you through all phases of this project and covers all the theoretical and technical details necessary for the creation of the final architecture and design. It places special emphasis on the research and development methodology utilized in the project. The methodology described in this book includes the following elements: creation of a candidate architecture, comparative testing on the functional level, selection and final refinement of the best architecture, transformation from the architecture level to the design level, logical and timing testing of the design, and presentation for fabrication. The text details how software tools are used in this project and how RISC architecture serves as the baseline for the project. It covers specific design techniques, languages, testing phases, architectural issues, implementation technology, and applications. The book, tested in a number of university courses and commercial tutorials, is ideal for various undergraduate courses devoted to microprocessor design for VLSI.
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adder algorithm ALU operation approach assembly language basic Belgrade benchmark bits branch instruction catalytic migration circuit clock cycle code optimization compiler complexity contains coprocessor DARPA decode defined Distributed Shared Memory dst=d DUMMY DUMMY E/D-MESFET ENDOT package example field flip-flops GaAs chips GaAs microprocessor GaAs technology gate hardware hardware description languages hazard high-level language IEEE Computer immediate operand implementation input instruction execution instruction fetch instruction set interconnect load instruction LOGSIM mask layers microprocessor Milutinovic MIPS for Star netlist nop instructions percent performance pipeline stage PL VLSI placement and routing prefabricated problem realization refers reg[dst register file RISC architecture RISC machine RISC processor SC VLSI methodology shown in Figure signal simulation solutions specified speed standard cell Star Wars structure SU-MIPS Symbol test vector Tomasevic transistor count UCB-RISC University of Belgrade VHDL VLSI chip VLSI design zero