System Level Design with Rosetta
The steady and unabated increase in the capacity of silicon has brought the semiconductor industry to a watershed challenge. Now a single chip can integrate a radio transceiver, a network interface, multimedia functions, all the "glue" needed to hold it together as well as a design that allows the hardware and software to be reconfigured for future applications. Such complex heterogeneous systems demand a different design methodology. A consortium of industrial and government labs have created a new language and a new design methodology to support this effort. Rosetta permits designers to specify requirements and constraints independent of their low level implementation and to integrate the designs of domains as distinct as digital and analog electronics, and the mechanical, optical, fluidic and thermal subsystems with which they interact.
In this book, Perry Alexander, one of the developers of Rosetta, provides a tutorial introduction to the language and the system-level design methodology it was designed to support.
* The first commercially published book on this system-level design language
* Teaches you all you need to know on how to specify, define, and generate models in Rosetta
* A presentation of complete case studies analyzing design trade-offs for power consumption, security requirements in a networking environment, and constraints for hardware/software co-design
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abstract actual parameters adder allows analysis anonymous function Antiderivative application argument assumptions AST structure basic begin behavior bitvector boolean bottom clause clk::input clock co-algebra complex component composition constant constructor correctness conditions discrete_time domain domain semi-lattice elements end facet interface engineering domains evaluation example export facet definition Figure finite_state firewall formal parameter FPGA func function composition function definition function value functional model functors higher-order functions i::input implementation implications increment infinite_state instantiated integer interaction interpretable function item declarations keyword language let expression multiset notation o::output package parameter list power constraint power consumption model properties radix point relationships represent result return type Rosetta functions Rosetta specification semi-lattice sequence setTime shared signature simply state_based domain state_type static domain subset subtype supertype syntactic sugar syntax system-level design TDMA tion true type assertion type inference Unicode units of semantics universally quantified parameters variable Verilog VHDL
Page xix - It is not even the beginning of the end. But it is, perhaps, the end of the beginning.