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Parallel Computer Architectures
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active records algorithm requires array locations assigned band-totals binary bit position bit-serial bitonic merge bitonic sort broadcast buckets calculated chip CLIP4 clock column consists constant of proportionality data items data-dependent descend algorithms distributed memory efficiently fetch-and-add full adder global Hough transform hypercube-derived computer IEEE image processing implemented input interconnection network intermediate destinations labeling large number logical processor loglog lookup MasPar memory computers mesh connected computer MIMD monotonic permutation multiple Nassimi neighbors node number of processors output pairs Parallel Algorithms parallel computers perform phase pixels plain hypercube computer plain mesh connected pointer PRAM processor-based processors puter pyramid computer random RAR algorithms RAR operations RAW and RAR result rithms router row-major row-major ordering scan operation Section segmented scan shared memory locations shifted significant bit SIMD simulation single solved sorted lists stages stored switches synchronous technique tion topology tree computer