The SPARC Architecture Manual: Version 9
David L. Weaver, Tom Germond
PTR Prentice Hall, 1994 - Computers - 357 pages
SPARC (Scalable Processor Architecture) is the industry's only openly defined and evolved RISC architecture. Version 9 is the new 64-bit incarnation of SPARC - the most significant change since SPARC's introduction in 1987! Unlike other RISC (Reduced Instruction Set Computer) designs, SPARC specifies not a hardware implementation ("chip"), but an open, standard architecture belonging to the community of SPARC vendors and users. The SPARC specification is defined by the SPARC Architecture Committee, a technical arm of the computer-maker consortium, SPARC International. Version 9 provides 64-bit data and addressing, support for fault tolerance, fast context switching, support for advanced compiler optimizations, efficient design for Superscalar processors, and a clean structure for modern operating systems. The V9 architecture supplements, rather than replaces, the 32-bit Version 8 architecture. The non-privileged features of Version 9 are upward-compatible from Version 8, so 32-bit application software can execute natively, without modification, on Version 9 systems - no special "compatibility mode" is required. Publication of the Version 9 architecture marks a three-year development effort by SPARC International member companies from a broad cross-section of disciplines.
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32 bits address space alternate space annul Appendix architecture Assembly Language Syntax atomic Branch byte cache CANRESTORE CANSAVE cause compare-and-swap Compatibility Note Dekker's algorithm division_by_zero doubleword effective address endian error_state example exception execution fccn field floating-point registers Format FPop global halfword hardware i_or_x_cc illegaljnstruction imm_asi impl Implementation Note implementation-dependent integer condition codes integer register interrupt request JMPL little-endian load/store loads and stores MAXTL mem_address_not_aligned MEMBAR instruction memory barrier memory model memory order memory transaction modify MOVcc nonprivileged operand OTHERWIN overflow performed prefetch processor program counter Programming Note PSTATE r[rd r[rsl rd op3 rs1 rdpr RED_state reg_or_imm register windows regrsl SAVE instruction self-modifying code sequential consistency signed integer SPARC SPARC-V9 specified Suggested Assembly Language supervisor software SWAP tion trap handler trap level trap type trap vector Unsigned word-aligned wrpr zero