The SPARC architecture manual: version 8
This in-depth guide to Version 8 SPARC, a high-speed RISC computer chip, provides the reader with the background, design philosophy, high-level features and implementations of this new model. Includes an expanded index of terms for easy reference and a table of synthetic instructions added to the suggested assembly language syntax.
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address space Alternate space annul Appendix Application Binary Interface Assembly Language Syntax atomic load-store bits Branch byte cache coprocessor deferred trap defined Dekker's algorithm delay instruction dividend division_by_zero divisor doubleword error exception executed Fault Status floating-point floating-point instruction FLUSH instruction Format fp_disabled FPop halfword hardware illegal_instruction Implementation Note implementation-dependent Instructions opcode op3 integer condition codes interrupt request iter JMPL LDSTUB load Memory Model modify icc multiply op3 rsl i-0 opcode op3 operation operand overflow physical address pointer processor Programming Note quad-precision r[rd r[rsl rd op3 rsl Reference MMU reg_or_imm register windows regrd regrsl result SDIVcc self-modifying code simml3 SPARC ABI software SPARC architecture SPARC implementations stack frame Status Register STBAR Suggested Assembly Language supervisor software SWAP Table Entry tag_overflow texc trap handler UMULcc UNIMP Unsigned Integer virtual address