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An ASIC Solution for HighPerformance
The Scalable Processor Architecture SPARC
A RISC Tutorial
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address space allows annul applications architec arithmetic benchmarks bits buffer byte cache chip CISC clock CMOS compiler condition codes conditional branch context switch coprocessor cycles per instruction debugging decoded defined fetch Figure floating-point instructions floating-point unit formats functions gate-array global registers hardware instruction set integer unit interface interrupt Invalidate kernel load and store load/store LSI Logic MBus memory microprocessor MIPS and SPARC module multiple multiprocessor Namjoo operating system optimization performance pipeline pointer Processor Architecture provides queue real-time register file register windows RISC architectures RISC machines SBus signal simulation single Smalltalk source operands SPARC architecture SPARC implementations SPARC International SPARC processor SPARC systems SPARCstation specified stack standard store instructions structions Sun Microsystems SunOS superscalar synchronization tagged thread thread-local storage tion trap handler UNIX vendors