What people are saying - Write a review
We haven't found any reviews in the usual places.
RSVPRapid System Visualization Prototyping
Experimental Results in Rapid System Prototyping with Incomplete
Design Verification Using Logic Tests
12 other sections not shown
Other editions - View all
address bus algorithm ALMA analysis Appendix application architecture behavior block diagram carrier compiler complex composition conceptual graphs contains context cursor Decision Table defined described design errors design verification detected device digital signal processor DMCR domain Durra Edited environment event example execution external component FADD FADD4 fault coverage Field Object Figure flowchart functional Galaxy graphical hardware hierarchical I/O tool IEEE Computer Society implementation input integrated interactions International ISBN keyboard label language logic mapping methodology MINIX module multilevel secure notation OBJ3 Object Instances operating system optic flow output Parallel Proto parameter performed primitive process nodes processor protocol provides rapid prototyping Rapid System Prototyping real-time representation requirements RSVP screen Sg estate SGUIM simulation Software Prototyping specification SRMop structure stuck-at fault synthesis system design task description techniques template Test Set testing coverage UIMS validation variable VHDL View