The Student's Guide to VHDL
The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.
Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised.
In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.
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Scalar Data Types and Operations
Composite Data Types and Operations
Basic Modeling Constructs
Packages and Use Clauses
Predefined and Standard Packages
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adder alias aliases architecture behavioral architecture body array type attribute begin Chapter clause clock clock signal complex_polar component instance concurrent condition configuration declaration constant defined delay described digit downto EBNF element type elsif end architecture end entity end loop end process end record entity declaration enumeration type example executed expression flipflop formal parameter FPGA function function function Gumnut hardware identifier IEEE implementation index range inout line instantiation integer interface keyword label literal logic logic value memory module next_state opcode operand operations output port overloaded package body package declaration port map predefined procedure reg4 represent reset resolved result return bit return bit_vector return boolean return unsigned scalar signal assignment statement signed simple_expression simulation specify std_ulogic std_ulogic_vector string subprogram subtype synchronous syntax rule synthesis tool to_string variable vector versions of VHDL wait statement waveform width write xmap xnor