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The Architecture and Engineering of Digital Computer Complexes, Volume 2
No preview available - 2013
accounting additional allocation allow alternate analysis assignment associated assume authority block buffer called channel characters command communication complex configuration connection considered cost cycle delay dependent determine device direct disc distribution drum effective efficiency elements entries example executive exist explicit extensive facilities fail failure Figure functions given graph hardware higher implemented increased independent initiated input instruction internal interrupt ledger length load logical malfunction matrix means memory node obtain occur operator output particular partition performance physical possible priority probability problem processing processor queue reason record recovery reduced redundant relation relatively request result schedule scheme sequence shown space specification statistics stored structure switching tape task termination tion transaction transfer transition typically units usually various viability executive