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adder Address Registers allows architecture arithmetic unit associated Atlas bits branch buffer register bytes cache central memory central processor clock period contains Control Point Control Register copied corresponding CYBER decoded delay descriptor destination digit doubleword element example execution rate figure floating-point addition floating-point unit FORTRAN functional units hardware highway IBM System/360 IBM System/360 Model ICL 2900 Series Increment index registers input operands Instruction Buffer instruction execution instruction format Instruction Pipeline Instruction Stack Instruction Word involves issued Jump Trace jump-to loaded loop machines main storage mantissa MFLOPS minor cycle Model 91 Multiply Unit Name Store normally occurs one-address operand accessing organisation output page fault performance pipeline pre-fetching processing PROP Register File requests result register scalar processor Scoreboard sequence sequential Shift stacking machine stage Store Access store word store-to-store orders string strobed updated vector instruction vector processor virtual address