The Architecture of High Performance Computers |
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adder Address Registers allows architecture arithmetic unit associated Atlas bits branch buffer register bytes cache central memory central processor clock period contains Control Point Control Register copied corresponding CYBER decoded delay descriptor digit example execution rate figure Floating-point Add floating-point unit FORTRAN functional units hardware highway hold-up IBM System/360 IBM System/360 Model ICL 2900 Series Increment index registers input operands Instruction Buffer instruction format Instruction Pipeline Instruction Stack Instruction Word involves issued Jump Trace jump-to length loaded loop machines main storage mantissa MFLOPS minor cycle Model 91 Multiply Unit Name Store normally occurs operand accessing organisation output page fault performance pipeline pre-fetching processing PROP Register File result register scalar processor Scoreboard sequence sequential Shift stacking machine stage Store Access store word store-to-store orders Stream Unit string Strobe TI ASC updated vector instruction vector processor virtual address