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HARDWARE DESIGN AND STAGE CASCADING
TIMING CONTROL AND PERFORMANCE
STATIC PIPELINED SYSTEMSVECTOR PROCESSORS
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adder algorithm approach architecture arithmetic pipeline assume average latency bandwidth basic bit vector bound buffer circuit clock column compatibility class complex conditional BRANCH configured decode delay depends diagonal dynamically E-unit element-by-element elements ENDOP equivalent example Figure floating-point gate greedy cycle handle hardware hazards hit ratio I-queue IBM System/360 IBM System/360 Model implementation initial collision vector input instruction set interleaved memory latency sequence Lemma logic loop main memory matrix memory access memory address memory module memory system microinstruction microprogram Model 91 modified state diagram multiplier needed nonpipelined number of stages occurs operands optimal output overlap parallel partitioning performance Pipelined Computers pipelined vector processor possible prefetch problem processing register files reservation table result sample scalar scalar processor SIMD single SISD staging latches storage struction techniques tion typical vector instruction vector operations vector processor words