The Cache Memory Book
The Second Edition of The Cache Memory Book introduces systems designers to the concepts behind cache design. The book teaches the basic cache concepts and more exotic techniques. It leads readers through someof the most intricate protocols used in complex multiprocessor caches. Written in an accessible, informal style, this text demystifies cache memory design by translating cache concepts and jargon into practical methodologies and real-life examples. It also provides adequate detail to serve as a reference book for ongoing work in cache memory design.
The Second Edition includes an updated and expanded glossary of cache memory terms and buzzwords. The book provides new real world applications of cache memory design and a new chapter on cache"tricks".
* Illustrates detailed example designs of caches
* Provides numerous examples in the form of block diagrams, timing waveforms, state tables, and code traces
* Defines and discusses more than 240 cache specific buzzwords, comparing in detail the relative merits of different design methodologies
* Includes an extensive glossary, complete with clear definitions, synonyms, and references to the appropriate text discussions
What people are saying - Write a review
We haven't found any reviews in the usual places.
What Is a Cache Memory?
How Are Caches Designed?
Cache Memories and RISC Processors
4 other sections not shown
Other editions - View all
address bits Address Buffers Address Tag bus traffic bytes cache controller cache data memory cache data RAM cache design cache directory cache line cache locations cache memory cache miss cache-tag RAM cache's cached copies chip clock concurrent line copy-back cache CPU write device direct data intervention direct-mapped Dirty line evicted fetch Figure Futurebus+ hit rate implement input Invalid line from owner LOAD logical cache main mem main memory bus main memory location matching memory management unit MESI MESI protocol miss cycle MOESI multiprocessor occur output performance primary cache problem processor read cycle Read Hit read miss response RISC secondary cache Section set address set bits snoop hit snoop-tag RAM speed SRAM static RAM status change status to Shared subroutine system bus tag bits Update line Update status Valid bit Valid Data write allocation write buffer write hit write miss Write to cache