The Design and Evaluation of a High Performance SmallTalk System
This book documents two results that run counter to conventional wisdom about the Smalltalk-80 system. It shows that a reduced instruction set computer (RISC) can offer excellent performance for a system with dynamic data typing, and that automatic storage reclamation need not be time-consuming.The Smalltalk-80 system makes it possible to write programs quickly by providing object-oriented programming, incremental compilation, run-time type checking, use-extensible data types and control structures, and an interactive graphical interface. However, the potential savings in programming effort have been curtailed by poor performance in widely-available computers or by high processor cost. To solve these problems, a group of researchers has designed and built the SOAR (Smalltalk on a RISC) microprocessor which is documented in this book.Their findings suggest that: the language-specific hardware in SOAR doubles its performance over a RISC II with the same cycle time; generation scavenging, a storage reclamation algorithm developed by the author, consumes only 3 percent of the CPU time, in contrast to the 9 percent of comparable Smalltalk-80 systems; and that the SOAR microprocessor should run as fast as an ECL Dorado minicomputer, despite a five-to-one handicap in basic cycle time. They also identify six features that substantially improve performance, as well as seven that contribute little to performance.Contents: Introduction. Previous Work. The SOAR Architecture. Performance Evaluation of the SOAR Architecture. Non-Disruptive High Performance Storage Reclamation. Scavenging Data with Intermediate Lifetimes. Conclusions. Appendix A: Detailed Performance Evaluation of Individual Features. Appendix B: Raw SOAR Data.David Ungar is an Assistant Professor in the Department of Electrical Engineering in the Computer Systems Laboratory at Stanford University. The Design and Evaluation of a High Performance Smalltalk System is a 1986 ACM Distinguished Dissertation.
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The SOAR Architecture
Performance Evaluation of the SOAR Architecture
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activation record architecture automatic storage reclamation barrel shifter benchmark Berkeley Smalltalk bytecodes chip compiler cost of omitting cycles per cycle deferred reference Dorado Evaluating exploratory programming environments fast shuffle feature Figure frequency full SOAR geu/outO hardware in-line cache insert omission cost insert/extract omission cost instruction set instructions cycles insts per inst jump load loadm Macro-Benchmark Execution Macro-Benchmark Instruction Mix main memory microcode nilling opcode overhead page faults pause personal computer pointers reference counting register windows regs retnw retnw's per return retw retw's RISC Scavenging Section shadow cost shadow registers simulator skip skip's per cycle skip's per instruction Smalltalk-80 system SOAR's space ST system static struction subroutine tag checking tag trap tagged immediate tagged stores taggedlmm tenuring threshold testActivationReturn testClassOrganizer testCompiler testPrintDefinition testPrintHierarchy trap handler trap instructions trap3 trapH cycles trapl untaggedlmm vectored traps virtual memory words Xerox Xerox PARC
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Memory Management: International Workshop IWMM 95, Kinross, UK, September 27 ...
Henry G. Baker
No preview available - 1995