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ASTA An Integrated System for BIST Analysis and Automatic Test Generation
Tools and Devices Supporting the PseudoExhaustive Test
Databases and Frameworks
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algorithm application architecture array assigned automatic automatic test pattern behavior blocks boolean bT-TOO cell channel chip circuit CMOS complex component Computer Computer-Aided Design connected constraints cycle data path data structure database defined delay described Design Automation Conference design data design environment design objects detected edge efficient elements example fault coverage fault simulation Figure floorplan formal verification framework function gate global graph hardware heuristic hierarchical high level synthesis IEEE implementation input integration interface layout logic Logic Synthesis machine mapping memory meta data method microprogram minimal module netlist node operations optimal output partitioning performance placement problem Proc procedure propagation router routing scheduling segments sequence signal simulated annealing simulation solution specific step stuck-on stuck-open faults subnetwork synthesis techniques test pattern testability tion transformations transistor variables verification vertices VHDL VLSI wire