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Reducing the Replacement Overhead in BusBased COMA Multiprocessors
Routing and Networks
A Performance Comparison of Hierarchical Ring and MeshConnected
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address space algorithm applications attraction memory bandwidth benchmarks bits block branch prediction bytes cache coherence cache line cache miss cessor COMA communication compiler Computer Architecture Cray T3D cycles distribution DMA engine DMA operation effect entry Ethernet evaluation execution fetch Figure global hardware IEEE ILP speedup implementation increase instruction invalidation kernel L2 cache Linesize load lock loop machine memory accesses memory latency memory pressure memory system mesh message proxy mispredicted multicast multiplexing multiprocessor multithreaded network interface node NUMA-RC operating system optimization overhead packet page table parallel parameters Pentium performance pipe pipeline prefetching primitives Proc protocol processor queries queue read miss reduce remote writes request ring scheme secondary cache Section shared memory shows simulation stall superscalar switch synchronization target tion transfer tuples U-Net update user-level DMA vector virtual channels VLIW write buffer write-write false sharing