Tutorial, distributed processor communication architecture: initially presented at the First International Conference on Distributed Computing Systems, October 1-4, 1979, Huntsville, Alabama
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DESIGN DECISIONSTHE TAXONOMY
FUTURE DIRECTIONS message A switching element affects
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AFIPS AFIPS Press allocation applications architecture ARPANET assignment bandwidth basic bits block buffer capability central channel circuit switching complexity computer architecture computer communication Computer Conf computer networks computer systems configuration connection cost crossbar crossbar switch crosspoints data communications data transfer datagram delay destination devices discussed distributed error example Figure flow control functions gateway hardware host IEEE implementation input interconnection interface internal logic memory microprocessors minicomputer modules Montvale multiple multiplexing multiprocessor munication node operating system optimal output packet switching path perfect shuffle performance problem Proc processing processor protocol puter queue routing algorithm Satellite IMP scheme Section sharing signal SIMD simulation slot Staran storage store-and-forward structure subnetwork switching network synchronous Tech techniques terminals throughput tion topology traffic trans transmission transmitted Unibus unit Univac updating utilization virtual circuit