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Decoupled AccessExecute Architectures
Very Long Instruction Word Architectures and the ELI512
Implementing Precise Interrupts in Pipelined Processors
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Alewife algorithm Amdahl apex applications array bandwidth banyan benchmarks bits block branch instructions branch prediction bytes cache coherence cache misses ccNUMA chip compiler Computer Architecture Computer Science Computer Systems consistency models context switching cost cycle developed efficient evaluation execution fetch fetch-and-add Figure fine-grain hardware HPSm IEEE implementation instruction set Intel interconnection International Symposium ISCA issue latency loop machine mance mechanism memory access microcode microprocessor multiprocessor network interface opcode operand operating system optimizations paper parallel parallel computer performance pipeline precise interrupts prefetch problem Proc processor Programming Languages protocol prototype queue reorder buffer Retrospective RISC scalable scheduling scheme sequential consistency shared memory simulation strategy stream buffers structure Symposium on Computer synchronization tion UNIBUS virtual memory VLIW VLSI Warp write