This text follows the tradition of Sze's highly successful pioneering text on VLSI technology and is updated with the latest advances in the field of microelectronic chip fabrication. Since computer chips are foundations of modern electronics, these topics are essential for the next generation of USLI technologies, allowing more transistors to be packaged on a single chip. Contributing to each chapter are industry experts, specializing in topics such as epitaxy with low temperature process, rapid thermal processes, low damage plasma reactive ion etching, fine line litography, cleaning technology, clean room technology, packing and reliability.
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Conventional and Rapid Thermal Processes
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annealing atoms beam BiCMOS bipolar bonding capacitance Chemical Vapor Deposition chip circuit cleaning cleanroom CMOS concentration contamination defects density deposition rate deposition temperature dielectric diffusion dopant doping DRAM electrical Electrochem electromigration Electron Dev energy epitaxial equipment FIGURE gases gate oxide growth heating IEEE Trans implant impurities increase interconnect interface ion implantation junction layer lithography LPCVD manufacturing mask material mechanism metal MOSFET Multilevel optical package parameters particles pattern PECVD photoresist planarization plasma etching poly poly-Si polycide polysilicon polysilicon films pressure production Rapid Thermal reactant reaction reactor reduced reliability resistance result S'S S'S S'S self-aligned semiconductor shown in Fig silane silicide silicon dioxide silicon nitride SiO2 sputtering step coverage stress structure substrate Tech techniques Technol thickness TiSi2 transistor typical ULSI VLSI voltage wafer wafer fab wire x-ray