Ultra Low Power Capacitive Sensor Interfaces
Springer Science & Business Media, Jun 15, 2007 - Technology & Engineering - 104 pages
The increasing performance of smart microsystems merging sensors, signal processing and wireless communication promises to have a pervasive impact during the coming decade. These autonomous microsystems nd applications in sport evaluation, health care, environmental monitoring and automotive s- tems. They gather data from the physical world, convert them to electrical form, compensate for interfering variables or non-linearities, and either act - rectly on them or transfer it to other systems. Most often, these sensor systems are developed for a speci c application. This approach leads to a high rec- rent design cost. A generic front-end architecture, where only the sensors and the microcontroller software are customized to the selected application, would reduce the costs signi cantly. This work presents a new generic architecture for autonomous sensor nodes. The modular design methodology provides a exible way to build a complete sensor interface out of con gurable blocks. The settings of these blocks can be optimized according to the varying needs of the application. Furthermore, the system can easily be expanded with new building blocks. The modular system is illustrated in a Generic Sensor Interface Chip (GSIC) for capa- tive sensors. Many con guration settings adapt the interface to a broad range of applications. The GSIC is optimized for ultra low power consumption. It achieves an ON-state current consumption of 40?A.
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53 Effective number of bits
6 Experimental results
61 Pressure monitoring system
62 Inclination monitoring system
7 Performance comparison
ALGORITHM FOR OPTIMAL CONFIGURATION SETTINGS
21 Fullscale loss
32 Operational ﬂow
GENERIC SENSOR INTERFACE CHIP
2 Capacitive sensors
3 Generic Sensor Interface Chip for capacitive sensors
31 Frontend architecture
32 CapacitancetoVoltage convertor
33 Chopping scheme
34 SC ampliﬁer
35 ΣΔ modulator
36 Bandgap reference bias system and buffered reference voltage
37 Main clock clock generation circuits and LF clock
4 Configuration settings
52 Noise calculations
Other editions - View all
1/f noise accelerometer activity monitoring system algorithm autonomous sensor nodes bandgap reference bandwidth becomes high becomes low bias circuits bias currents bits buffered reference voltage C-V converters Capacitance-to-Voltage capacitive sensor interface cascode charge injection clock frequency clock generation circuits CMOS component configurable blocks configuration flag configuration settings Cref current consumption digital output code duty cycle feedback capacitor Figure Fmod full-scale loss function Furthermore GSIC Hence Ibias implemented input leakage error LF clock main clock main oscillator microcontroller modular noise of switch non-linearity offset op-amp optimal performance physical activity monitoring power consumption pressure sensor programmed quantizer readout reduce reference and bias reset sample frequency sample timer SC amplifier SC interface sensor applications sensor interface chip sensor nodes sensor system settling error signal phase temperature transistors Ultra Low Power Uout Vin+ virtual ground voltage voltage-to-current converter Vout Vref ΣΔ
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