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Binary Addition and Subtraction
BCD Subtraction Division and Fractions
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2's complement accumulator addend addition applied arithmetic arrangement augend basic binary digits binary number buffer register carry chip circuit clock cycle clock pulse complement adder/subtracter configuration connected control section core data bit data bus data flow data input decimal digit decimal numbers decimal-to-binary encoder decoder delay demultiplexer depicted in Figure digital data digital words display device divisor driven logic-high employed example FF's flip-flop full adder goes logic-high Hewlett-Packard inhibit line input lines input pulse instruction inverter JK flip-flop line is driven loaded logic level logic-low memory microinstruction microprocessor system multiplexer negative numbers nibble Note operation output lines parallel four-bit parity plane program counter PROM Q output quotient readout reference to Figure reset ring counter sense line sequence seven-segment display shift register shown in Figure Sign bit signals storage stored subtraction terminal tion tri-state buffers trigger truth table voltage waveform XOR gate