Using WAVES and VHDL for Effective Design and Testing: A Practical and Useful Tutorial and Application Guide for the Waveform and Vector Exchange Specification (WAVES)
The proliferation and growth of Electronic Design Automation (EDA) has spawned many diverse and interesting technologies. One of the most prominent of these technologies is the VHSIC Hardware Description Language, or VHDL.
VHDL permits designers of digital modules, components, systems, and even networks to describe their designs both structurally and behaviorally. VHDL also allows simulation of the designs in order to investigate their performance prior to actually implementing them in hardware.
Having gained the ability to simulate designs once encoded in VHDL, designers were naturally confronted with the issue of testing these designs. VHDL did not explicitly address the requirement to insert particular digital waveforms, often termed test vectors or patterns, or to subsequently assess the correctness of the response from some digital entity.
In a distributed design environment, or even in an isolated one where the design was subject to review or scrutiny by another organization, de-facto methods of testing and evaluating results proved faulty. The reason was a lack of standardization. When organization A designed a circuit and tested it with their self-developed test tools it had a certain behavior. When it was delivered to organization B and B tested it using their test tools, the behavior was different. Was the fault in the circuit, in A's tools, or in B's tools? The only way to resolve this was for both organizations to agree on a test apparatus, validate its correctness and use it consistently.
While VHDL was an IEEE standard language, and consistency among myriad designers was fairly well guaranteed, no such standard existed for test waveform generation and assessment. Hence, the value of standardization in the design language was being negated by the lack of such a standard for testing.
The Waveform and Vector Exchange Specification, or WAVES, was conceived and designed to solve this testing problem – and it has. Being both a subset of VHDL itself, as well as an IEEE standard, it guarantees both conformity among multiple applications and easy integration with VHDL units under test (UUTs).
Using WAVES and VHDL for Effective Design and Testing will serve many purposes. For the WAVES beginner, its tutorial will make the application of WAVES in typical, standard usage straightforward and convenient. For the more advanced user, the advanced topics will provide insight into the nuances of these useful capabilities. For all users, the tools, templates and examples given in the chapters, as well as on the companion disk, will provide a practical starting foundation for using WAVES and VHDL.
What people are saying - Write a review
We haven't found any reviews in the usual places.
Figure No Title Page
The History and Background of WAVES
20 other sections not shown
Other editions - View all
actual apply Automatic Test Equipment begin Compatible CONSTANT constructs context clauses D-type flip-flop Data Input define describe Design and Testing device dont_care drive formats drive_L edge transitions edge1 edge2 edgel edgeO electronic design automation elements entity etime example external file frame elist frame event frame set array function hardware Hardware Description Language header file IEEE STD implementation integration k k k library WAVES_1164 logic level logic simulation logic value system new_frame set ēr ēr ēr output parity_output pattern data pin codes pinset pulse high RETURN frame set reusable Rome Laboratory simulation environment specific Std ulogic std_logic stimulus test vectors utilizing vector file VHDL model waveform concepts waveform generator procedure waveform shapes waveform signals WAVES and VHDL WAVES building blocks WAVES dataset WAVES files WAVES Level WAVES Packages WAVES standard WAVES testbench Waves_Interface Waves_Objects package Waves_Port_List WAVES-VHDL simulation