VHDL answers to frequently asked questions
VHDL Answers to Frequently Asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp.lang.vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complex simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL. This book differs from other VHDL books in many respects. This book: emphasizes real VHDL, rather than philosophical or introductory types of information emphasizes application of VHDL for synthesis uses complete examples to demonstrate problems and solutions provides a disk that includes all the book examples and other useful reference VHDL material uses easy to remember symbology notation to emphasize language rules, good and poor methodology and coding styles identifies obsolete VHDL constructs that must be avoided identifies synthesizable/non-synthesizable structures uses a question and answer format to clarify and emphasize the concerns of VHDL users.
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Address architecture ASIC assert False report barrel shifter begin wait Bit Vector BOOLEAN BOOLEAN BOOLEAN Bus Protocol BusOut Clk'event and Clk clock Cntlr compiler concurrent signal assignment concurrent statements configuration declaration constant constrained conversion function defined demonstrates element elsif emacs end component end loop end process entity error injector example Fault injection formal parameter formal verification global signal IEEE.Std_Logic_1164.all inout input Integer range interface LFSR library IEEE Logic Vector memory MISR Multiple Drivers ns Iteration object operator output port map pragma process begin process variable RamLink random RdWrF regression tests Reset return return return return SIGNED return STD sensitivity list severity Note shown in figure simulation Std Logic Std_Logic_Vector Std_Logic_Vector(7 downto Std_uLogic Std.TextlO.Write(L_v subprogram subtype Synopsys synthesis synths Test Test_Lbl testbench tri-state Type conversion ulogic unconstrained array UNSIGNED VHDL wait statement wait until Clk'event