VHDL for Simulation, Synthesis and Formal Proofs of Hardware
Springer US, May 31, 1992 - Computers - 307 pages
The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.
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abstraction algorithm architecture ASIC behavior block boolean capacitance CDFG circuit clock component Computer concurrent Concurrent Pascal cycle data transformation defined delay Delay Calculation described design process diagrams embedded systems end process END-ENTITY entity event example execution Figure formal verification function gate graph hardware description language hardware design hierarchy high-level synthesis IEEE implementation inout input instantiation integer interface logic synthesis logic synthesis tools loop machine multi-value logic nclr node operations outc output package partitioning performed port Preprocessor procedure process statement Proofs of Hardware propagation register transfer level represent representation reset result SA-VHDL scheduling semantics smax source code specification standard structure subl SUBTYPE switch synchronous Synthesis and Formal synthesis process synthesis system Synthesis View system level TC(0 downto token transistor transition triplet variable vdrn VHDL code VHDL description VHDL for Simulation VHDL model VHDL process VHDL simulation vsrc WAIT statement