VHDL Techniques, Experiments, and Caveats
VHDL (VHSIC Hardware Description Language) is the market-leading digital circuit simulation software system. Now a VHDL expert offers readers the benefits of his in-depth experience as a VHDL modeler and seminar leader. Packed with a huge array of examples, this book presents a pragmatic picture of VHDL that takes full account of its possibilities and its limitations.
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Driving the Simulation Flow
Predefined Signal Attributes
VHDL Techniques and Recommendations
6 other sections not shown
algorithm architecture body array assert statement associated attribute Author i Joaeph begin wait Behave_1 BIT_VECTOR BOOLEAN Clock'EVENT code for experiment compiler concurrent signal assignment Count Count_3_Bit Current_Count Current_State data type Datain Dataout default delta time unit design entity downto element Encapsulate_3_Bit_Count end Behave end proceaa entity declaration enumeration literal enumeration type error event executed Expected observations FALSE Figure File Name flip-flop global variables Hence ia end incrementation inefficiency initial value initialization phase input instantiation INTEGER Joseph Pick entity Logic Logic4 Logic4_Vector lookup table ment Objective occur ordered pair package parameter port map problem projected driver PULSE_WIDTH queue Recommended solution reserved word resolution function scheduled Signal_A simulation cycle simulation engine Source code specific std_ulogic subprogram subtype technique tion trailing edge updated variable Vector VHDL journeys VHDL language VHDL model VHDL tool suite wait statement wait until Clock waveform write