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VLSI Processor Architecture
A Survey of Parallel Computer Architectures
Efficient Embeddings of Binary Trees in VLSI Arrays
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adder algorithm binary tree buffer carry look-ahead adder cells chip circuit clock cycle command communication complexity component Computer Science connected data compression data path decode delay delete dictionary machine digit DRA2 edge example execution function Gaussian graph H. T. Kung hardware IEEE Trans implementation index space input insert instruction set interconnection ISBN iteration Kung label layout slices leaf node Leiserson Lemma linear network logic lower bound mapping match matrix memory microcode MIPS multiple operands operation optimal output parallel parallel computation partitioning PE's performance pipeline pixel pointer prenetwork priority queue problem Proc processing elements processor array proposed query response result root scale-space scheme Section segment semantic network shortest path problem shown in Fig SIMD structure symbol systolic array technique tile tion transformation transitive closure variables vector VLSI architectures VLSI array wavefront