Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them

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Springer Science & Business Media, Apr 30, 2010 - Technology & Engineering - 218 pages
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In programming, “Gotcha” is a well known term. A gotcha is a language feature, which, if misused, causes unexpected - and, in hardware design, potentially disastrous - behavior. The purpose of this book is to enable engineers to write better Verilog/SystemVerilog design and verification code, and to deliver digital designs to market more quickly.

This book shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize these common coding mistakes, and know how to avoid them. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug the errors.

This book is unique because while there are many books that teach the language, and a few that try to teach coding style, no other book addresses how to recognize and avoid coding errors with these languages.

 

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Contents

Foreword by Steve Golson
1
Chapter
3
Chapter
7
Implicit net declarations
10
Default of 1 bit internal nets
13
Single file versus multifile compilation of Sunk declarations
15
Local variable declarations
17
Escaped names in hierarchical paths
19
Operator evaluation short circuiting
116
The not operator versus the invert operator
118
Array method operations
119
Array method operations on an array subset
121
Chapter
123
Nested if else blocks
128
Evaluation of equality with 4state values
129
Event trigger race conditions
131

Hierarchical references to automatic variables
22
Hierarchical references to variables in unnamed blocks
25
Hierarchical references to imported package items
27
Importing enumerated types from packages
28
Importing from multiple packages
29
Default base of literal integers
30
Signedness of literal integers
32
Signed literal integers zero extend to their specified size
33
Literal integer size mismatch in assignments
35
Filling vectors with all ones
37
Array literals versus concatenations
38
Port connection rules
39
Backdriven ports
43
Passing real floating point numbers through ports
46
Chapter
49
Arrays in sensitivity lists
52
Vectors in sequential logic sensitivity lists
54
Operations in sensitivity lists
56
Sequential logic blocks with begin end groups
57
Sequential logic blocks with resets
59
Asynchronous setreset flipflop for simulation and synthesis
60
Blocking assignments in sequential procedural blocks
62
Sequential logic that requires blocking assignments
64
Nonblocking assignments in combinational logic
66
Combinational logic assignments in the wrong order
70
Casezcasex masks in case expressions
72
Incomplete decision statements
74
Overlapped decision statements
77
Inappropriate use of unique case statements
79
Resetting 2state models
82
Locked state machines modeled with enumerated types
84
Hidden design problems with 4state logic
86
Hidden design problems using 2state types
88
Hidden problems with outofbounds array access
90
Outofbounds assignments to enumerated types
92
Undetected shared variables in modules
94
Undetected shared variables in interfaces and packages
96
Chapter
98
Selfdetermined versus contextdetermined operators
101
Operation size and sign extension in assignment statements
105
Signed arithmetic rules
108
Bitselect and partselect operations
111
Increment decrement and assignment operators
112
Preincrement versus postincrement operations
113
Modifying a variable multiple times in one statement
115
Using semaphores for synchronization
134
Using mailboxes for synchronization
137
Triggering on clocking blocks
139
Misplaced semicolons after decision statements
140
Misplaced semicolons in for loops
142
Infinite for loops
144
Locked simulation due to concurrent for loops
145
Referencing for loop control variables
147
Default function return size
148
Taskfunction arguments with default values
150
Continuous assignments with delays cancel glitches
151
Chapter
153
Using interfaces with objectoriented testbenches
155
All objects in mailbox come out with the same values
157
Passing handles to methods using input versus ref arguments
158
Constructing an array of objects
159
Static tasks and functions are not reentrant
160
Static versus automatic variable initialization
162
Forked programming threads need automatic variables
164
Disable fork kills too many threads
166
Disabling a statement block stops more than intended
168
Simulation exits prematurely before tests complete
171
Chapter
173
Undetected randomization failures
175
Sassertoff could disable randomization
177
Boolean constraints on more than two random variables
179
Unwanted negative values in random values
181
Coverage reports default to groups not bins
182
Coverage is always reported as 0
184
The coverage report lumps all instances together
186
Covergroup argument directions are sticky
187
Assertion pass statements execute with a vacuous success
188
Concurrent assertions in procedural blocks
190
Mismatch in assert else statements
192
Assertions that cannot fail
193
Chapter
195
Package chaining
198
Random number generator is not consistent across tools
200
Loading memories modeled with always_latchalways_ff
202
Nonstandard language extensions
204
Array literals versus concatenations
206
Module ports that pass floating point values real types
208
Index
209
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