Proceedings of the 1986 International Conference on Parallel Processing: August 19-22, 1986
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Interconnection Networks I
Equivalence Between CubeConnected Cycles Networks and Circular Shuffle
The Sneptree A Versatile Interconnection Network
81 other sections not shown
algorithm analysis approximation architecture array assume average bandwidth banyan banyan network binary tree block Cayley graph CC-banyan cells circuit circuit switched combining communication complete binary tree Computer Science concurrency configuration connected crossbar cycle defined delay distributed efficiency equations evaluation example execution fan-in fanout fault fault-tolerant Figure FORTRAN function Gaussian elimination hardware HCSN network hot spot IEEE IEEE Trans implementation leaf node linear loop machine mapping matrix matrix multiplication memory modules mesh MIMD multiplication multiprocessor number of processors omega network optimal output port packet switched paper parallel computation Parallel Processing parameters partition path performance permutation phase pipelined pivot problem Proc quadtree queue recursive requests routing shared memory shown SIMD simulation Sneptree speedup stage structure SW-banyan switching elements systolic array task techniques tion topology traffic transaction tree saturation variable vector VLSI wait buffer