ISA System Architecture

Front Cover
Addison-Wesley Professional, 1995 - Computers - 515 pages

"An invaluable tool and reference on ISA architecture and time reading it is time well spent. You might just end up wondering how you ever got along without it!"

-David Greenberg, Dell Computer Corporation

ISA System Architecture describes the hardware architecture of ISA (Industry Standard Architecture), providing a clear, concise explanation of an ISA system in detail. The authors provide a comprehensive treatment of the bus including:

  • bus cycles
  • addressing
  • I/O
  • RAM, ROM, and cache memory
  • cache architectures
  • decode and reset logic
  • interrupts
  • system kernel
  • bus mastering
  • DMA
  • RTC and configuration RAM

If you design or test hardware or software that involves ISA, ISA System Architecture is an essential, time-saving tool.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

0201409968B04062001

 

Selected pages

Contents

III
9
IV
19
V
27
VI
37
VII
51
VIII
105
IX
111
X
117
XVIII
271
XIX
313
XX
331
XXII
333
XXIII
349
XXIV
363
XXV
407
XXVI
431

XI
137
XII
151
XIII
189
XIV
219
XV
231
XVII
233
XXVII
439
XXVIII
447
XXIX
457
XXX
467
Copyright

Other editions - View all

ISA System Architecture
Tom Shanley,Don Anderson,MindShare, Inc
Snippet view - 1995
ISA System Architecture
Tom Shanley,Don Anderson,MindShare, Inc
Snippet view - 1995

Common terms and phrases

16-bit device 80286 microprocessor address bus address decoder address latch address lines address space asserted bus control logic bus cycle bus cycle definition bus master bus unit buses cache controller cache memory chip-select CHRDY clock column address coprocessor CPU READY data bus data bus steering data bus transceivers deasserted DMA channel DMAC doubleword DRAM DRAM addressing DRAM chip DRAM memory EEPROM execution unit fetch four bytes I/O address I/O device I/O port input instruction Intel interface interrupt controller interrupt request interrupt service routine interrupt table ISA bus ISA systems keyboard lower data path M/IO main memory memory address memory location memory read micro microproces microprocessor mode DRAM MRDC MWTC Numeric Coprocessor operation output parity PCLK perform prefetch processor protected mode read bus cycle real mode Refer to figure SBHE segment register stack subsystem system board table entry virtual 8086 mode

Bibliographic information

TitleISA System Architecture
Mindshare PC System Architecture
PC system architecture series
AuthorsTom Shanley, Don Anderson, MindShare, Inc
EditorJohn Swindle
Editionillustrated
PublisherAddison-Wesley Professional, 1995
ISBN0201409968, 9780201409963
Length515 pages
Subjects ›  › 

Computers / Computer Architecture
Computers / Networking / General
Computers / Networking / Hardware
Technology & Engineering / Electrical
  
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