Synthesis Techniques and Optimizations for Reconfigurable SystemsSynthesis Techniques and Optimization for Reconfigurable Systems discusses methods used to model reconfigurable applications at the system level, many of which could be incorporated directly into modern compilers. The book also discusses a framework for reconfigurable system synthesis, which bridges the gap between application-level compiler analysis and high-level device synthesis. The development of this framework (discussed in Chapter 5), and the creation of application analysis which further optimize its output (discussed in Chapters 7, 8, and 9), represent over four years of rigorous investigation within UCLA's Embedded and Reconfigurable Laboratory (ERLab) and UCSB's Extensible, Programmable and Reconfigirable Embedded SystemS (ExPRESS) Group. The research of these systems has not yet matured, and we continually strive to develop data and methods, which will extend the collective understanding of reconfigurable system synthesis. Synthesis Techniques and Optimization for Reconfigurable Systems assumes a basic understanding of logic design, hardware synthesis (from high-level architecture generation down to placement and routing), and the structure and form of high-level application constructs (such as loops and branches). However, this book may be read and used in the absence of such background knowledge. This text is aimed at researchers and system-level designers (both academic and industrial), but could easily be used as the text of graduate-level course on reconfigurable system synthesis techniques. |
Contents
INTRODUCTION | 1 |
SYNTHESIS OF DIGITAL SYSTEMS | 5 |
RECONFIGURABLE SYSTEMS | 15 |
MODELS OF COMPUTATION | 55 |
A FRAMEWORK FOR SYSTEM SYNTHESIS | 85 |
HARDWARESOFTWARE SYSTEM PARTITIONING | 107 |
INSTRUCTION GENERATION | 127 |
DATA COMMUNICATION | 175 |
INCREASING HARDWARE PARALLELISM | 213 |
Acknowledgments | 221 |
| 222 | |
| 243 | |
Other editions - View all
Synthesis Techniques and Optimizations for Reconfigurable Systems Ryan Kastner,Adam Kaplan,Majid Sarrafzadeh No preview available - 2010 |
Common terms and phrases
ADD ADD Additionally amount APCSG application architecture level array ASIC basic block behavioral benchmarks CDFG chip circuit clustering compiler complexity components Configuration Bit constraints control flow control nodes cost Custom Computing Machines D-function D-node data communication dataflow dominance frontier edge type embedded systems entity Esterel execution Field-Programmable Figure floorplan FPGA gate global hardware heuristic IEEE Comput implement input instruction interconnect iteration language latency Lemma level of abstraction loop memory microarchitecture microprocessor minimize model of computation operations optimizations output pair of vertices Parallel Template partitioning problem performance placement platform Proceedings processor programmable devices programmable logic programmable logic devices pruned algorithm reconfigurable architectures reconfigurable computing reconfigurable devices reconfigurable systems representation Sequential Template spatial specific SUIF superblock Symposium synthesis task techniques Template Generation Algorithm trace scheduling transitive closure variable vertex VHDL VPBS Xilinx
Popular passages
Page 223 - JR Hauser and J. Wawrzynek. GARP: A mips processor with a reconfigurable coprocessor.
Page 223 - N. Park and AC Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans, on CAD, 7(3), 1988. [16] P. Pochmuller, M. Glesner, and F. Longsen. High-Level Synthesis Transformations for Programmable Architectures. EuroDAC '93, 1993. [17] R. Potasman, J. Lis, A. Nicolau, and D. Gajski. Percolation Based Synthesis.