## Computer Arithmetic: Volume IThe book provides many of the basic papers in computer arithmetic. These papers describe the concepts and basic operations (in the words of the original developers) that would be useful to the designers of computers and embedded systems. Although the main focus is on the basic operations of addition, multiplication and division, advanced concepts such as logarithmic arithmetic and the calculations of elementary functions are also covered. This volume is part of a 3 volume set: Computer Arithmetic Volume IComputer Arithmetic Volume II Computer Arithmetic Volume III The full set is available for sale in a print-only version. Contents:OverviewAdditionParalReadership: Graduate students and research professionals interested in computer arithmetic.Key Features:It reprints the classic papersIt covers the basic arithmetic operationsIt does this in the words of the creatorsKeywords:Computer Arithmetic;Adders;Parallel Prefix Adders;Multi-operand Adders;Multipliers;Dividers; |

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### Contents

Burla | 37 |

PARALLEL PREFIX ADDITION | 75 |

MULTIOPERAND ADDITION | 99 |

Chen | 118 |

MULTIPLICATION | 119 |

H Garcia | 145 |

237 | 155 |

E E Swartzlander Jr The QuasiSerial Multiplier | 161 |

LOGARITHMS | 217 |

J C Majithia and D Levan A Note on Base2 Logarithm Computations | 231 |

A Wooley | 237 |

ELEMENTARY FUNCTIONS | 243 |

J S Walther A Unified Algorithm for Elementary Functions | 318 |

FLOATINGPOINT ARITHMETIC | 319 |

IBM System Journal vol 4 pp 3142 1965 | 339 |

S F Anderson J G Earle R E Goldschmidt and D M Powers The | 351 |

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### Common terms and phrases

addition algorithm approximation arithmetic unit binary logarithms binary numbers binary point bit position carry look-ahead adder carry propagation carry-save adders circuit circuitry column convergence CORDIC cycle decoding delay described digital computers dividend division methods divisor Electronics equations error evaluation example execution factor fan-out fanout floating-point fraction full adder functions gates hardware high-order IEEE IEEE Trans implementation integer iteration layout least significant log2 logarithm logic low-order matrix maximum multiplicand negative normalization number of bits number of inputs number system obtained operand operations output paper parallel multipliers partial algorithm partial product partial remainder performed polynomial quasi-serial quotient digit radix radix point range READ-ONLY memory reduced result ripple-carry adder rotation scheme sequence shift shown in Fig signal significant bit speed stage step subtraction summands Table technique tion two's complement vector VLSI xxxx xxxx xxxx zero