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Considerations for implementing a conformance test program
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20 ns Hold accompanying diskette Aligned Address arbitration owner Arbitration waveform asserted INTERLOCK asserted SETUP backplane BICS pro forma Capacitive loading CONFORMANCE Table connection phase Data Length Data Width Delay RQ0 describes a special describes a test Description Timing value disconnection phase found in file FUTUREBUS+ Std Header File IEEE STANDARD ISO/IEC issue.crq IUT Cache Slave IUT Master IUT Slave last data beat Lock Command Multiple Packet Normal status TEST_ID ns 20 ns ns IUT ns na 20 Number Description odd data beat Paragraph parallel protocol parity error pass competition Phase 5 Phase Propagation Delay Read Invalid read transaction Read Unlocked released HOLD released INTERLOCK released to aq requesting module REQUIREMENTS FOR FUTUREBUS+ signal slot special test pattern Split Response STANDARD FOR CONFORMANCE subclause TEST REQUIREMENTS TEST_NAME tester violates normal transaction This waveform violates normal Futurebus+ waveform describes write transaction Write Unlocked