Highly Parallel Signal Processing ArchitecturesKeith Bromley |
Contents
HARDWARE IMPLEMENTATION ISSUES | 97 |
SOFTWAREPROGRAMMING ISSUES | 117 |
OPTICAL MATRIX PROCESSORS | 145 |
Copyright | |
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Common terms and phrases
achieve adder addition algebra algorithm allow Analysis applications approach architectures arithmetic assignment binary bits called cell channel checksum chip circuit column communication complex computation concurrent consider convolution correct corresponding Cout decomposition defined described detection detector developed direction discussed efficiency elements encoding error example execution fault Fault-Tolerant Figure function given hardware IEEE implementation important inner input integrating iterative language light linear machine matrix memory methods module multiplication names node operations optical output parallel partial performed plane present primitives problem Proc processor redundancy represent result rotation scheme shown Signal Processing single singular value solution solve space speed square step structure systolic array Table techniques tolerance Transform triangular unit vector VLSI wavefront weighted ם ם