Proceedings, Volumes 1-2IEEE Computer Society Press, 2005 - Computer storage devices |
Contents
Y Cai L Fang R Ratemo J Liu K Gross M Kozma | 661 |
Test Connections Tying Application to Process | 679 |
11716757 | 690 |
Copyright | |
49 other sections not shown
Other editions - View all
Common terms and phrases
applied architecture ATPG BICR bits block Boundary-Scan burn-in calibration capture chip circuit clock CMOS column compaction compactor compression Computer configuration core cycles decoder delay fault detection device diagnosis DUT board embedded failing failure fault coverage fault simulation flip-flop FPGA function gate hardware IEEE implemented input interface International Test Conference jitter JTAG latches leakage linear load logic logic value masking matrix memory method methodology MISR mode multiple n-detection node noise NPDF operation output overhead path performance pins Proc propagation proposed PRPG pulse reduce scan cells scan chains scanout Section sequence SerDes shown in Figure signal simulation soft error SRAM stuck-at faults Table target techniques temperature test algorithm test patterns test response test set test system test vectors tester transient transistors transition VirtualScan VLSI voltage waveform