Analog-digital Simulation of Transient-induced Logic Errors and Upset Susceptibility of an Advanced Control SystemNational Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1990 - Digital avionics - 10 pages |
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2100 transient injections 9 pC advanced avionics control Aeronautics and Space Analog-Digital Simulation Carreno cause external pin characteristics charge level CMOS Compute value control loop control unit countdown decoder unit describes a simulation digital simulation electrical transients produce electrical transients resulting error propagation FAULT INJECTION Figure first-order errors Flow diagram Functional errors functional units gate-level description gate-transistor Hamilton Standard incorporates fault-tolerant techniques Injection node injections are analyzed integrated circuit intermodule Langley Research Center large-scale integrated latched-error propagation logic values memory microprocessor monitors multiplexer NASA National Aeronautics nsec order errors output parameters parity percent Performing Organization program flow analysis R. K. Iyer Read sensor recovery mechanisms Results for 2100 sient injection simulation run software testing Space Administration system being tested system under test system upset tems three gate distances tran transistor level Transistor models type of error upset mode Upset Susceptibility upset testing Upset-Assessment value sensor watchdog and control watchdog unit