Evaluation, Implementation, and Enhancement of the Dispatch Stack Instruction Issuing Mechanism |
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Contents
Description of the Dispatch Stack | 16 |
Enhancements to the Dispatch Stack | 107 |
Conclusions and Future Directions | 126 |
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2P 4P FP algorithm approach architecture assembly language benchmarks branch instructions branch outcomes concurrency extraction concurrent execution condition code conditional branch Configuration conflict(i content addressable data dependencies Data Memory decremented delays dependency information destination register detection Dispatch Stack DS[infinf dynamic code scheduling dynamic scheduling EBUS elimination enhancing execution resources Execution Unit fetch count fetch phase fields Figure FP modes functional unit processors hand-compilation hardware immediate operand implementation instruction issuing mechanism instruction set instruction window instructions per cycle issued per cycle issuing instructions look-ahead loop machine memory access multiple functional unit multiple instructions non-sequential number of instructions partial order PEBUS peephole optimizations performance PFPIPE pipelined PLEBUS PPARA Program in 2.12 PXBAR redundant computations redundant load register allocation register renaming Section sequential serial execution stream shadow effects simulator source registers speedup static scheduling Table techniques Throughput Instructions/Cycle tion Tjaden Tomasulo's transitive closure update phase useless assignments VECTRAN