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Technical and Industrial Challenges for Signal Processing in Consumer
T A C M Claasen
Specification Partitioning and Design of a DAB Channel Decoder
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adder algorithm applications architecture ASIC block buffer cells chip circuit coefficients communication complexity components computation constraints CORDIC decoding delay digital signal Digital Signal Processing efficient equation error estimation example execution factor FPGAs frequency function hardware high level synthesis IDCT IEEE IEEE Trans image processing implementation input instruction cycles integrated interface iteration latency linear loop macro macroblock matrix memory method minimal module multiplier node noise operations optimization parallel parameters partitioning path performance pipelined pixel problem Proc processor array QR decomposition quantization real-time realization registers rotations router sample scheduling SDF graph sequence shown in Figure Signal Processing SIMD simulation soft output specification structure subband synchronous synthesis systolic array techniques throughput transformations two's complement unit update vector VHDL Viterbi Viterbi algorithm Viterbi decoder VLSI wordlength