Introduction to Formal Hardware VerificationHardware verification is a hot topic in circuit and system design due to rising circuit complexity. This advanced textbook presents an almost complete overview of techniques for hardware verification. It covers all approaches used in existing tools, such as binary and word-level decision diagrams, symbolic methods for equivalence checking, and temporal logic model checking, and introduces the use of higher-order logic theorem proving for verifying circuit correctness. It enables the reader to understand the advantages and limitations of each technique. Each chapter contains an introduction and a summary as well as a section for the advanced reader. Thus a broad audience is addressed, from beginners in system design to experts. |
Contents
| 1 | |
Boolean Functions | 31 |
Approaches Based on Finite State Machines | 83 |
Propositional Temporal Logics | 151 |
HigherOrder Logics | 207 |
Appendix A Mathematical Basics | 255 |
Appendix B Axioms and Rules for CTL | 267 |
| 277 | |
| 291 | |
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Common terms and phrases
abstraction level according to Def algorithm aligning sequence applied approaches automata automated axioms becomes true behavior Binary Decision Diagrams bit vectors Boolean functions characteristic function cofactor combinational circuits complete construction contain corresponding CTL model checking defined Definition denotes efficient elements equivalence checking Example existential quantification exists fairness constraints faults finite state machines formal specification formal verification function ƒ function tables function value gate given graph hardware verification Hence higher-order logic holds implementation input sequence input values iteration linear LTL formula modules natural numbers nodes OFDD order logic output function pairs path formula possible predicates product automaton proof goal properties propositional logic propositional temporal logics Q₁ reachable recursive representation represented requires reset sequence ROBDD rules Sat(Q satisfiability semantics sequential circuits shown subset successor t₁ tableau techniques temporal logic temporal operators temporal structures Theorem tion transition relation traversal variable ordering variants x₁