Economies of Scale in Semiconductor Manufacturing: How to Achieve and to DestroyMaster's Thesis from the year 2004 in the subject Business economics - Business Management, Corporate Governance, grade: gut, Donau-Universität Krems, course: MBA Entrepreneurship, language: English, abstract: During my work for semiconductor companies I had the possibility to deeply get in touch with semiconductor industry and with fabrication lines (FAB’s) being operated at different sizes with different product technologies. Especially benchmarking activity with other semiconductor companies and FAB’s gave me the possibility to understand the mechanisms behind efficiency of semiconductor fabrication lines. In most of observed cases economies of scale are promised to have a great effect on production costs, which in general is true. However it happens that, especially when benchmarking different FAB’s against each other, smaller FAB’s are not that costly as estimated. Looking at them with magnifying glasses shows up methods how to achieve economies of scale even for smaller fabrication lines. However to understand the difference and the real lever for low manufacturing costs intrinsic analysis are necessary. The details of each of these analysis is property of the companies, however within this thesis I generalized the results obtained in the past and removed lots of numbers and facts, without removing the key message. Thus lots of graphs in this figure show numbers, that either have been turned from absolute to relative numbers or falsified numbers in order not to include any company critical information. Since understanding semiconductor industry is an intrinsic task, also basic rules of this kind of industry are included inside this thesis. This allows readers from other branches to understand the terminology and to get a good broad picture of thisindustry, at least for the present decade. Since evolution is very fast, certain things will certainly change along the years, however general truths can be applied anytime. The general aim of this thesis is not to dig very deep inside a certain FAB effi- ciency problem. It is moreover to enlist a big variety of possible influences blocking efficiencies that are believed to be earned with increasing FAB size. For the detailed few on the single efficiency levers and blockers references are enlisted in the back of the thesis. My personal experience shows that alone with these various detailed scientific papers it is very hard to translate the problems to a level, where they can be approached in real life. I hope this thesis help in understanding the economies of scale levers in the semiconductor industry in an sufficient but easy and convenient way. |
