Intel Memory Design Handbook |
Contents
16K RAM Refresh Modes 24 | 24 |
troduction | 10-35 |
nother MOS Levet Drivers | 11-5 |
5 other sections not shown
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Common terms and phrases
16K RAM 4K RAMs A.C. Characteristics address input battery Bipolar bit sense line Block Diagram capacitance capacitor charge chip enable chip select clock driver CMOS cycle refresh data cycles DATA INPUT data output data rate decoupling deselected DOUT driver power dynamic RAM four-phase clock gate input/output Intel latch logic Low Voltage maximum memory array memory cycle memory devices memory system minimum MOS level multiplexer node Note nsec Open Collector operation output buffer PD/PGM pin configuration POLYSILICON power dissipation power supply printed circuit board program pulse PROM random access memory Read Cycle read only memories refresh address refresh cycle refresh mode resistor sense amplifier shift cycles SHIFT EXECUTE shown in Figure signal static RAM storage cell Supply Current SUPPORT CIRCUITS switch Symbol Parameter Table transistor Typical Unit Test volt Waveforms write cycle