Symbolic model checking

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Kluwer Academic, 1993 - Technology & Engineering - 194 pages
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Formal verification means having a mathematical model of asystem, a language for specifying desired properties of the system ina concise, comprehensible and unambiguous way, and a method of proofto verify that the specified properties are satisfied. When the methodof proof is carried out substantially by machine, we speak ofautomatic verification. "Symbolic Model Checking" deals withmethods of automatic verification as applied to computerhardware.The practical motivation for study in this area is the high andincreasing cost of correcting design errors in VLSI technologies.There is a growing demand for design methodologies that can yieldcorrect designs on the first fabrication run. Moreover, design errorsthat are discovered before fabrication can also be quite costly, interms of engineering effort required to correct the error, and theresulting impact on development schedules. Aside from pure costconsiderations, there is also a need on the theoretical side toprovide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoreticalattention.

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