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Mapping Algorithms to Parallel Systems
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Proceedings 20th International Conference Parallel Processing 1991, Volume 2
Limited preview - 1991
algorithm allocation architecture array bandwidth barrier binary block broadcast buffer cache coherence cessor clock Clos network cluster communication Computer Computer Architecture connected Cray Y-MP cycle dataflow delay destination efficiency execution fault Figure functional units global graph hardware HL order hypercube hypermesh I/O scheduling IEEE IEEE Trans implementation input interconnection network interleaved iteration latency load loop machine mapping matrix memory access memory modules memory system MIMD multiple multiprocessor n-cube node number of processors operations optimal output overhead packet parallel computer Parallel Processing parallel program path PC-graph perfect shuffle performance permutation pipeline port prefetch prime cube problem Proc protocol reconfiguration request routing scalar scheduling scheme sequence shared memory shown SIMD simulation speculative execution stage subcube subtree Supercomputing superscalar switch synchronization task techniques Theorem threads tion token queue traffic tree Univ vector vector processing VLIW