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23 INXH addr address bus address lines ADREGL arithmetic ASCII asynchronous binary block buffers busses byte CALL instruction chip clock control signals CPU module CRPPI data bus data transfer decoder Direct Memory Access display DMAC enable EPROM example execution external device flip flop floppy disk flow chart FUNCTION GPIB group of instructions Hex code HLDA hold request I/O device INITIALISE INPUT Input/Output instruction set Intel's interface devices interrupt request IX+d IY+d latch logic LOOP LOOP1 LOOP2 LXI H machine cycle master memory address memory location microprocessor system Mnemonic mode multibus operation output polling loop port priority processor Programme Variables PROM pulse register pair RESET SCANDIS scheme scratch pad registers shown in Fig specified status stored string subroutine Table terminal two's complement USART