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Keynote Address and Invited Speakers Table
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1985 International Test algorithm analysis applied automatic test Automatic Test Pattern Automation backtracking bit-slice calibration cells chip clock CMOS combinational conflict resolution cost delay fault detection device device under test diagnostics Digital equipment error example fanout fault coverage fault simulation flip functional test gate GIPS hardware IEEE implementation interface International Test Conference LFSR logic logic values manufacturing measure memory method node operation Paper path PEAT performance port primary inputs probability probe problem Proc propagation random test reconvergent fanout scan selected self-test sensitive sequential circuit shift register shown in Figure signal specific Table techniques Teradyne test area test counts test length test pattern test program test set test system test vectors testability tester tion transistor transition VLSI voltage wafer watchdog XOR gate