Proceedings, IEEE International Conference on Computer Design: VLSI in Computers : Rye Town Hilton, Port Chester, New York, October 31-November 3, 1983
IEEE Computer Society Press, 1983 - Technology & Engineering - 764 pages
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addition algorithm allows analysis applications approach architecture array block called cell channel chip circuit clock CMOS compiler complexity components connected consists contains cost cycle defined delay described determined device effective elements engineering error example execution expression failure fault Figure function gate given hardware IEEE implementation increase input instruction integrated interconnection internal language layout length logic machine memory method module multiplier node operation output parameters path patterns performance placement possible present problem procedure processor provides reduced reference represented routing segments selected shown shows signal simulation single specific speed step structure switch symbolic Table techniques tion transistor unit VLSI wire