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2's complement address space algorithm allows ALOHANET architecture arithmetic ARPANET ARRAY FIELD bit-slice bits block branch buffer bytes C.mmp cache channel Chap chip circuit communication complete components computer space concurrency core store cycle data-types DECODE descriptor devices diagram digits Dmap drum example execution units fetch floating point floating-point function hardware Illiac Illiac IV implementation input instruction Instruction prefetch interconnection interface interrupt load logic loop memory MENEHUNE microcode microinstruction microprogram microword mode modules multiple multiplexer multiprocessor nodes operand operating system output packet performance pipeline Pluribus port processor Q register queue request segment selected sequence sequential shift shown in Fig signal slice stack STARAN storage structure subroutine switch Table tape techniques tion transfer vector virtual machine virtual memory word zero