Retargetable Code Generation for Digital Signal Processors
According to market analysts, the market for consumer electronics will con tinue to grow at a rate higher than that of electronic systems in general. The consumer market can be characterized by rapidly growing complexities of appli cations and a rather short market window. As a result, more and more complex designs have to be completed in shrinking time frames. A key concept for coping with such stringent requirements is re-use. Since the re-use of completely fixed large hardware blocks is limited to subproblems of system-level applications (for example MPEG-2), flexible, programmable pro cessors are being used as building blocks for more and more designs. Processors provide a unique combination offeatures: they provide flexibility and re-use. The processors used in consumer electronics are, however, in many cases dif ferent from those that are used for screen and keyboard-based equipment, such as PCs. For the consumer market in particular, efficiency of the product plays a dominating role. Hence, processor architectures for these applications are usually highly-optimized and tailored towards a certain application domain.
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12 HWSW CODESIGN OF EMBEDDED SYSTEMS
13 EMBEDDED SOFTWARE DEVELOPMENT
14 DSP ALGORITHMS AND ARCHITECTURES
15 PROBLEMS AND SOLUTION APPROACH
16 OVERVIEW OF RELATED WORK
17 GOALS AND OUTLINE OF THE BOOK
42 PROGRAM REPRESENTATIONS
43 RELATED WORK
44 THE CODE GENERATION PROCEDURE
45 DFL LANGUAGE ELEMENTS
46 INTERMEDIATE REPRESENTATION
47 CODE SELECTION BY TREE PARSING
48 RT SCHEDULING
22 THE MSSQ COMPILER
23 APPLICATION STUDIES
32 ANALYSIS OF CONTROL SIGNALS
33 BINARY DECISION DIAGRAMS
34 INSTRUCTIONSET MODEL
35 INTERNAL PROCESSOR MODEL
36 BEHAVIORAL ANALYSIS
37 STRUCTURAL ANALYSIS
39 EXPERIMENTAL RESULTS
310 ISE AS A VALIDATION PROCEDURE
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access graph ACCU address assignment address register AGU operations algorithm AR[ARP architectures array references ASIP background register basic block behavioral modules binary Boolean function code compaction code quality code selection computed constraints control signals control steps cost data moves data-flow data-path delay lines denotes DFTs DSP algorithms edges embedded embedded systems encoded ETAs evaluates exploitation expression tree GRTPs guarded assignments hardware heuristic input instruction format instruction set instruction word instruction-level parallelism instruction-set extraction iteration language loop machine code MEM[AR[ARP memory MIMOLA mode register module variable modulo addressing MSSQ multiply-accumulate nodes NOPs optimal outp output partial instructions problem processor model REG.R register allocation register files register transfer representation retargetable compilers ring buffer RT expression RT patterns RT scheduling rules source code specification standard DSPs structure subtree target processor tree grammar tree parser tree parsing vertical code
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