Retargetable Code Generation for Digital Signal Processors

Front Cover
Springer Science & Business Media, Jun 30, 1997 - Computers - 210 pages
According to market analysts, the market for consumer electronics will con tinue to grow at a rate higher than that of electronic systems in general. The consumer market can be characterized by rapidly growing complexities of appli cations and a rather short market window. As a result, more and more complex designs have to be completed in shrinking time frames. A key concept for coping with such stringent requirements is re-use. Since the re-use of completely fixed large hardware blocks is limited to subproblems of system-level applications (for example MPEG-2), flexible, programmable pro cessors are being used as building blocks for more and more designs. Processors provide a unique combination offeatures: they provide flexibility and re-use. The processors used in consumer electronics are, however, in many cases dif ferent from those that are used for screen and keyboard-based equipment, such as PCs. For the consumer market in particular, efficiency of the product plays a dominating role. Hence, processor architectures for these applications are usually highly-optimized and tailored towards a certain application domain.
 

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Contents

INTRODUCTION
1
12 HWSW CODESIGN OF EMBEDDED SYSTEMS
2
13 EMBEDDED SOFTWARE DEVELOPMENT
5
14 DSP ALGORITHMS AND ARCHITECTURES
8
15 PROBLEMS AND SOLUTION APPROACH
14
16 OVERVIEW OF RELATED WORK
18
17 GOALS AND OUTLINE OF THE BOOK
27
PROCESSOR MODELLING
29
CODE GENERATION
85
42 PROGRAM REPRESENTATIONS
86
43 RELATED WORK
89
44 THE CODE GENERATION PROCEDURE
91
45 DFL LANGUAGE ELEMENTS
95
46 INTERMEDIATE REPRESENTATION
98
47 CODE SELECTION BY TREE PARSING
105
48 RT SCHEDULING
118

22 THE MSSQ COMPILER
33
23 APPLICATION STUDIES
36
INSTRUCTIONSET EXTRACTION
45
32 ANALYSIS OF CONTROL SIGNALS
48
33 BINARY DECISION DIAGRAMS
51
34 INSTRUCTIONSET MODEL
52
35 INTERNAL PROCESSOR MODEL
59
36 BEHAVIORAL ANALYSIS
60
37 STRUCTURAL ANALYSIS
68
38 POSTPROCESSING
78
39 EXPERIMENTAL RESULTS
80
310 ISE AS A VALIDATION PROCEDURE
82
INSTRUCTIONLEVEL PARALLELISM
127
52 GENERIC AGU MODEL
130
53 ADDRESSING SCALAR VARIABLES
132
54 ARRAYS AND DELAY LINES
146
55 CODE COMPACTION
161
THE RECORD COMPILER
179
62 CODE QUALITY
184
CONCLUSIONS
191
72 FUTURE RESEARCH
193
REFERENCES
195
INDEX
207
Copyright

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