74 pages matching Section in this book
Results 1-3 of 74
What people are saying - Write a review
We haven't found any reviews in the usual places.
Embedded FloatingPoint Units in FPGAs
Improving Performance and Robustness of DomainSpecific CPLDs
10 other sections not shown
3D-FPGA algorithm Altera application approach ASIC average baseline benchmarks bits BRAMs buffer cells circuit CLBs clock frequency clock network CMOL CMOS components computation configuration constraint core cost CPLD critical path crossbar switch cycle decoder delay devices dynamic power embedded memory block embedded multiplier erasure evaluation exploration Field-Programmable Gate Arrays floating-point FPGA Gate Arrays global hardware hash function IEEE implementation improvement increase input interconnect iteration key schedule L3 cache latency layer logic block logic synthesis module selection MRAM multiplexer nanowire netlist nodes operations optimal output parameters pattern pattern-matching performance pipeline placed and routed placement power consumption power gating programmable reconfigurable reconfigurable computing reduced registers resource sharing routing scheduling Section shifter shown in Figure signals simulation slices soft processors sparse crossbars SRAM standby Stratix structure switch Table techniques technology mapping tile transistors wires Xilinx