## Computer logic, testing, and verification |

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### Contents

Logic Minimization | 1 |

Acyclic Logic | 40 |

Acyclic Testing | 59 |

Copyright | |

5 other sections not shown

### Common terms and phrases

2-input 2-level acyclic logic design algor assigned assumed Boolean calculus cells Chapter chip coface combo product compute a test consists contains coordinates cost cubical complex cyclic D-algorithm D-chain D-frontier D-interface defined delay Delay Calculation denote disjoint equivalent example extraction algorithm extremals fan-in feed function hardware high-level IBM System/360 IBM Technical Disclosure IEEE IEEE Transactions implementation incomplete algorithms indeterminacies input pattern input variables interconnection interface iterative levels of logic lexicographical order logic block LSSD macro method minimum cover module multiple-output notation OFF-cover operation output variables pdcf PL/I PL/R primary input primary output prime cubes primitive D-cube problem R-FILE realization registers regular design regular logic design Roth RTRAN Section sequence sequential shift-register simulation single-output singular cube specification Technical Disclosure Bulletin test cube TESTDETECT tests for failures tion transform VERIFY vertices Watson Research Center Yorktown Heights