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The Architectures of HTM
Evaluation of HTM Design Space
3 other sections not shown
32 CPUs abort abort handler architecture atomicity bandwidth bayes benchmarks bits Bloom filter breakdown of STAMP buffer cache line closed-nested CM policy coherence protocol commit handler commit scheme conditional synchronization contention management continuous transactions cycles detect conflicts EP and LP EP-OLDEST evaluate Execution time breakdown false sharing Figure genome hardware implement instructions interconnect intruder invalidate kmeans labyrinth Lazy-Optimistic livelock LO-BASE loads and stores locks log writes LogTM mechanisms MESI mp3d multicore nested transactions nesting level Normalized to sequential open-nested transactions overhead parallel pathologies performance pessimistic conflict detection processor programming programming languages read-set roll back scheme Section semantics sequential execution serializable similar speculative speedup ssca2 STAMP applications STMs system calls system code TCC-BACK TCC-BASE TCC-UPDATE TCC-WORD thread tion TM design TM systems trans transaction commit transactional memory two-phase commit undo log update vacation Violate Stall violation handler virtualization write-set yada